DDR4 memory is found on most personal computers. The next generation memory standard is coming out. Computers users expect increased performance and optimal power consumption in the new chips.
If we focus on raw data, the main changes include a reduction in the voltage from 1.2V to 1.1V, and the 8n prefetch buffer will be replaced by 16n prefetch buffers, i.e. 16 bits per hour will migrate from memory cells to the IO buffer, while performance will be scaled from 3.2 Gbps to 6.4 Gbps per I/O connection.
We can expect increased performance as some memory makers have managed to enhance JEDEC specifications for DDR4.
The design of the DDR5 memory modules is based on 288 needles. The application of DDR5 will requires a new platform. The DIMM has been divided into two channels. A memory module offers two 32-bit channels, of which there will be twice 40 bits with ECC.
Between 8 bytes to 16 bytes the minimum stroke length varies. Sense a module uses two channels, it means it can double the data per operations(64x2). However, it must be remembered that these channels are not wide like channels in DDR4. So in DDR5 manufacturers have increased banking groups from four to eight and makes it possible to update the memory bank if others are working. This allows unused banks to be used sooner, maximizing the availability of less wide channels.
This is a helpful change,but not enough to double the performance in comparison to the DDR4.This requires increasing the memory bus clock speed, which DDR5 does when applying DFE, i.e. decision feedback equalization.Virtually this changed the DDR4 memory bus, reducing the amount of interference., which provided an adequate foundation to achieve a higher rate of data transfer with sufficient stability.
In terms of voltage control, JEDEC has also introduced a major innovation.Starting with the DDR5 standard, each memory module has its own voltage check. So this load is removed from the shoulders of the motherboards.
This is of great importance, because when designing motherboards, manufacturers always had to plan for the maximum possible memory configuration, while in many cases the purchased memory package did not even come close to the load for which the system was theoretically prepared, and this made the production of more modern motherboards quite expensive.
Of course, it can be immediately exclaimed that with the new specifications the costs of making memory modules will increase, but it is not negligible that the power supply of the system will become realistically predictable. From now on, it is enough to put on a memory module a regulator with the capability that is just enough to operate in a stable way, so that the fundamentally wasteful overdesign is eliminated. However, useful information may be that from DDR5 onwards, it has become pointless to purchase expensive motherboards designed for memory tuning, since increasing the memory clock speed will depend solely on the capabilities of the module and cpu memory controller. Of course, there will be no need to fear the motherboard manufacturers, this little problem will certainly be bridged with the wonderful power of marketing.